1. Technical Field
The present invention relates to oscillator circuits and related methods, especially phase locked loops with ring oscillators.
2. Description of Related Art
Phase-locked loops (“PLLs”) which incorporate voltage-controlled oscillators (“VCOs”) are used in a variety of applications, such as to perform channel selection and associated tuning in frequency-division multiplexed systems for radio, television, cable and satellite broadcast systems. In particular cases, the phase-locked loop may need to maintain the frequency output by a voltage-controlled oscillator (“VCO”) for a very long period of time. In a serial data transmission system which can be implemented in an integrated circuit of a semiconductor element such as a chip, for example, transmission and receiving frequencies may need to remain locked over an entire operating lifetime of the chip.
FIG. 1 is a block and schematic diagram illustrating a PLL 30 with coarse calibrating circuitry in accordance with the prior art. The VCO 32 includes a linear amplifier LA and a resonator including an LC tank circuit. A reference clock frequency (REFCLK) and a divider setting (% N) set the output frequency fL to be maintained by the VCO 32. In some applications such as for use in an intrasystem or inter-system serial data communications receiver, the PLL is expected to remain locked at a single output frequency fL over the entire lifetime of the PLL and the chip in which it is incorporated. In such case, the settings REFCLK and % N remain fixed throughout the lifetime of the chip. Viewed from left to right in FIG. 1, the PLL incorporates a phase-frequency discriminator PFD which produces an error signal 34 based on the difference between the frequencies of REFCLK and a feedback clock signal FBCLK obtained by dividing the output frequency fL with divider (% N). The error signal, typically in form of pulses, is input to a charge pump QP. The charge pump QP integrates the pulses and outputs a signal which is conditioned by a low-pass filter (LPF) to produce a control voltage CV at the input to the VCO 32. For coarse calibration, the charge pump QP produces a common mode voltage level CMV which is a neutral value of the control voltage.
The common mode voltage CMV and the control voltage CV are input to a coarse calibration circuit 36 which contains first and second comparators CN and CP and a circuit 38 to determine a minimum value CVmin and a maximum value CVmax that the control voltage can reach during operation of the PLL. The output COMPM of Comparator CN is activated when CV falls below CVmin. The output COMPP of Comparator CP is activated when CV rises above CVmax. During a coarse calibration operation, these signals COMPN and COMPP indicate whether the control voltage CV falls below the voltage CVmin, is between CVmin and CVmax, or rises above CVmax.
As further shown in FIG. 1, a PLL logic block 40 controls operation of the PLL by selecting the frequency band of the VCO operation through a band selection signal VBANDSEL<3:0> provided to the LC Tank circuit. During coarse calibration, REFCLK and the % N inputs are established and maintained and the PLL logic 40 sets the LC Tank to a given frequency band, which may be the lowest frequency band for the PLL. The PLL then begins operating at a given control voltage CV, which can be at the low end of its range, i.e., at around CVmin. As the PLL then works to make FBCLK equal to REFCLK, the control voltage CV increases over time by operation of the phase frequency discriminator PFD and the charge pump QP. If COMPP becomes active, indicating that CV exceeds CVmax, the required output frequency fL is not found within the selected frequency band. The PLL logic then selects a different frequency band, typically the next higher frequency band, and then performs the foregoing actions again with such frequency band to determine if the required frequency fL can be attained and locked within that frequency band. On the other hand, if the required frequency fL is achieved and the current control voltage value is not beyond the low end CVmin or high end CVmax of its range, a lock point, i.e., the required output frequency, can be achieved within the currently selected frequency band of the PLL.
However, even when the lock point is detected to be within one of the operating frequency bands of the PLL, coarse calibration operation is not finished yet. The PLL illustrated in FIG. 1 is designed to determine the frequency band for which the final control voltage is nearest to the neutral level (the common mode voltage CMV). Thus, when such lock point is detected, the current value of the control voltage CV is saved by the PLL logic 40, as well as signals representing the current CVmax and CVmin values. After the lock point is detected in one operating frequency band, the PLL is switched to one or more other operating frequency bands and the foregoing actions are repeated to determine whether the lock point is achieved within such other operating frequency bands. When the lock point is detected, the current value of the control voltage CV is again saved by the PLL logic 40, as well as signals representing the current CVmax and CVmin values. When all the frequency bands have been determined in which the lock point is achieved, the PLL logic then selects an operating frequency band for which the lock point is closest to the center of the range between CVmin and CVmax for that operating frequency band. The PLL then begins operating with that selected frequency band and is intended to stay within that selected band.
Further improvements are desirable in relation to background systems and methods.